These are my personal notes from when I was taking UCI's EECS119, which teaches VLSI design using Cadence Virtuoso.

When taking the course, I found the way most existing online tutorials teach Virtuoso to be overly simplistic, and after getting some usage experience it didn't seem like how the software was meant to be used. I had to figure a lot of this out by trial and error, and wanted to save others the trouble for the future. (This obviously doesn't cover everything and I'm still not an expert, but should be helpful for those in EECS119 or just starting out with VLSI with Virtuoso).

General

• Push v for vertical cursor in ADE visualization window
• Directory for loading techfile on the EECS servers for EECS119 & EECS170C labs
  • How to find the path of your home directory: cd ~/ && pwd

[YOUR HOME DIRECTORY]/eecs119/ncsu-cdk-1.6.0.beta/techfile

Schematic

• Connect outputs of circuit testbench to the noConn component from the basic library. Eliminates DRC error about unconnected node.

Layout Tips

• Use wires (Not Rectangles) to connect components/instances: ctrl+shift+w
• Insert your custom components like normal components into the layout, and connect them by drawing onto their metal traces.
  • When you draw your inner components leave space at the end of the trace the pins are on to connect to.
• To view location of errors in Layout DRC: Verify -> Markers -> Find Markers

Layout EZ Mode (Generating from Source)

• From schematic, open LayoutXL
• In layout XL, go to bottom of screen and click on "generate all from source"
• LayoutXL will autogen pins, instances of nmos/cmos, and all you have to do is line them up
• To the right of that button, "Show/Hide incomplete nets" button. Select everything, and then click that to generate lines that go between the things you need to connect.
• See screenshots below for more information.

Source-Generated Layout Tips

• One issue with generating from source is it sometimes won't recognize that certain nodes on the circuit are connected, and will keep the lines between them alive even though they're connected.
• LVS help - "Check against source"
  • Bottom row - green checkmark button. Extracts and checks against schematic, but highlights and tells you what's wrong. Doesn't get all errors, and can be tempermental.

Screenshots

All of the below Software screenshots were taken in LayoutXL.

Create wire

Generate all from source

Place components as in schematic

Show/hide selected incomplete nets

• This is one of the most useful options in LayoutXL. It creates a ratsnest between your traces similar to how PCB layout works, making connecting your components much easier.

  

Layout showing NAND gates placed as components in a standard cell layout, with wires going between them.

3 input JK Flip-flop (used in EECS119 HW3)

fish

Helpful Links

• Guide to Drawing Clean Schematics with Virtuoso
• Cadence Troubleshooting Guide